FPGA study note: Gate-level combinational circuit (1)

Note: This serial FPGA study note is not suitable for no programming experience learner.

Let’s start with a 1-bit comparator:



library ieee;
use ieee.std_logi_1164.all;
entity eq1 is port (
i0,i1: in std_logic;
eq: out std_logic);
end eq1;

architecture sop_arch of eq1 is     
signal p0,p1: std_logic;begin     
   eq <= p0 or p1;     
p0<= (not i0)  and (not i1);   
   p1<= i0 and i1;
end sop_arc;

1 basic lexical rules

VHDL is case insensitive, which means that upper- and lowercase letters can be used  interchangeably, and free formatting, which means that spaces and blank lines can be inserted freely.

For habit, we reserve uppercase letters for constants.

An identiJier is the name of an object and is composed of 26 letters, digits, and the underscore (-) , The identifier must start with a letter.

                — comments

2 library and package

The package and library allow us to add additional types, operators, functions, etc. to VHDL.

3 Entity declaration

The basic format for an I/O port declaration is

        signal-namel, signal-name2, . . . : mode data-type;

Mode can be : in , out or inout(bidirectional)

entity eq1 is

     Port (

    i0,i1: in std_logic;

    eq: out std_logic


End eq1;

4 Data type and operators

VHDL is a strongly typed language, which means that an object must have a data type and only the defined values and operations can be applied to the object

std-logic type  which is defined in the std_logic_1164 package and consists of nine values.

Three of the values, ’ 0 ’ , ’ I ’ , and ’ Z ’ , which stand for logical 0, logical 1, and high impedance, can be synthesized. Two values, ’U’ and ’X’ , which stand for “uninitialized” and “unknown” (e.g., when signals with ’ 0’ and ’ 1 ’ values are tied together), may be encountered in simulation.

The std_logic_vector data type, which is defined as an arrary with elements of std_logic, can be used for a signal in a digital circuit containing multiple bits.

Ex.  An 8-bit imput port :

a : in std-logic-vector ( 7 downto 0 ) ;

Logical operators

Including not,and,or,xor

Ex: a and b

5 Architecture body

Describing operation of the circuit.

The signal on the left-hand side of a statements can be considered as the output of that part.

This study note is from the book of Pong P. CHU. “FPGA Prototyping by VHDL examples”

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Dr. Lu