Selected signal assignment statement

The simplified syntax of a selected signal assignment statement is

with sel select
sig <= value_expr_1 when choise_1;
value_expr_2 when choise_2;
value_expr_3 when choise_3;
...
value_expr_n when others;

It assigns an expression to a signal according to the value of the sel signal. The others term is always needed to cover the unsynthesizable values(‘X’,’U’, etc.).

signal sel: std_logic_vector(1 downto 0);
...
with sel select 
r<= a+b+c   when "00"",
a-b     when "10",
c+1     when others;

It implies a 2²-to-1 multiplexer with sel as the selection signal, as shown in Figure 1.  Figure 1

Note that all value expressions are evaluated concurrently.

Ex

architecture sel_arch of prio_encoder is 
begin 
with r select 
pcode <= "100" when "1000" | "1001" | "1010" | "1011" | "1100" | "1101" | "1110" | "1111",
<= "011" when "0100" | "0101" | "0110" | "0111",
<= "010" when "0010" | "0011" ,
<= "001" when "0001",
<= "000" when others;  -- r="0000"
end sel_arch;

The entity declaration is identical to previous post(FPGA study note: RT-level combinational circuit(4)).