FPGA study note: RT-level combinational circuit(7)

if statement


if boolean_expr_1 then 
  sequential_statements;
elseif boolean_expr_2 then 
 sequential_statements;
elseif boolean_expr_3 then
sequential_statements;
...
else 
sequential_statements;
end if;

The Boolean expressions are evaluated sequentially until an expression is evaluated as true or the else branch is reached.

r <= a + b + c 
when m=n else a - b
when m>0 else c + 1;  

can be rewritten as

process(a,b,c,m,n)
begin 
  if m = n then 
     r <= a + b + c; 
elseif m > 0 then 
     r <= a-b;
  else
     r <= c+1;
  end if;
end;

architecture if_arch of prio_encoder is
begin
 process(r)
 begin
   if (r(4)='1') then
      pcode <= "100";
   elseif (r(3)='1') then
      pcode <= "011";
   elseif (r(2)='1') then
      pcode <= "010";
   elseif (r(1)='1') then
      pcode <= "001";
   else
      pcode <= "000";
   end if;
 end process;
end if_arch;

This codes written with an if statement are similar to those in the privous post.

News Reporter
Dr. Lu

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