Several previous study note show that the conditional and selected signal assignment statements can be rewritted by the simple if and case statements.

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;
large <= a when a > b else b;
small <= b when a > b else a;

Since there are two comparators in code. However, the same function can be coded by a single if statement:


process(a,b)
begin 
  if a> b then
    large <= a;
    small <= b;
 else 
    large <= b;
    small <= a;
 end if;
end;

Only one relational operator in code.

Although a process is flexible, a unitended memory problem may be occured(The VHDL standard specifies that a signal will kepp its previous value if it is not assigned in a process).
It’s better to follow these rules below while developing code for a combinational cirucit:

  1. include all input signals in the sensitivity list.
  2. include the else branch in an if statement.
  3. assign a value to every signal in every branch.
News Reporter
Dr. Lu

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