VHDL provides a construct, named as a generic, to pass information into an entity and component. it functions somewhat like a constant because a generic cannot be modified inside the architecture. A generic is declared inside an entity declaration, just before the port declaration:

entity entity_name is 
generic_name: data_type := defuat_values;
generic_name: data_type := defuat_values;
generic_name: data_type := defuat_values;
port_name: mode data_type;
end entity_name;

The previous adder code can be rewritted with a generic:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity gen_add_w_carry is 
generic (N : integer:= 4);
a,b: in std_logic_vector(N-1 downto 0);
cout: out std_logic;
sum: out std_logic_vector(N-1 downto 0);
end gen_add_w_carry;
architecture arch of gen_add_w_carry is 
signal a_ext, b_ext, sum_ext: unsigned( N downto 0);

As a constant, we can assign the desired value to the generic in component instantiation. This is known as generic mapping.
For example:

signal a4, b4, sum4: unsigned (3 downto 0);
signal a8, b8, sum8: unsigned(7 downto 0);
signal a16, b16, sum16:unsigned(15 downto 0);
signal c4, c8, c16:std_logic;
-- instantiate 8-bit adder
adder_8_unit: word.gen_add_w_carry(arch)
generic map(N => 8)
port map (a=>a8,b=>b8,cout=>c8,sum=>sum8);
-- instantiate 16-bit adder
adder_16_unit: word.gen_add_w_carry(arch)
generic map(N => 16)
port map (a=>a16,b=>b16,cout=>c16,sum=>sum16);
-- instantiate 4-bit adder
-- generic mapping omitted, default value 4 used
port map (a=>a4,b=>b4,cout=>c4,sum=>sum4);

A generic provides a mechanism to create scalable code. This makes code more portable and encourages design reuse.

News Reporter
Dr. Lu

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