The module is the basic unit in Verilog. It can describe the functionality or structure of a design and also describe the ports through which it communicates externally with other modules.
Here is the basic syntax of a module:
module module_name(port_list); declarations: reg,wire,parameter, input,output,inout, function,task,... Statements: initial statement always statement module instantiation gate instantiation UDP instantiation continuous assignment endmodule
Declaration are used to define the various items, such as registers and parameters, used within the module.
Statements are used to define the functionality or structure of the design.
Note that a declaration must appear before its use. It is recommended to put all declaration before any statements.
Give you a example of a module that models the half-adder circuit:
module HalfAdder (A, B, Carry); input A, B; output Sum, Carry;
assign #2 Sum = A^B;
assign #5 Carry = A&B;
Within a module, a design can be described in the styles:
1. Dataflow style
2. Behavioral style
3. Structural style
4. Any mix of above
These verilog tutorial is a study note of the book A verilog HDL Primer.