Step-by-step design process for microprocessors and FPGAs

Source : http://www.embedded.com/design/prototyping-and-development/4006429/FPGA-programming-step-by-step

 

FPGA

Architectural design

Choice of language   (Verilog, VHDL)

Editing programs

Compiling programs

Synthesizing programs
   (.EDIF)

Placing and routing programs
   (.VO, .SDF, .TTF)

Loading programs to FPGA

Debugging FPGA programs

Documenting programs

Delivering programs

 

Compiling

 

The analogous operation in FPGA programming is the compilation of Verilog into register transfer logic (RTL) netlists. As the name implies, data is transferred into registers, subject to some clocking condition. At this stage FPGA programming departs from microprocessor programming in that an additional synthesis process is required to produce bits (or intermediate objects that can be converted to bits) that will control gates and fill registers and memories on an FPGA. This level is called gate-level logic, since it describes the logical gates of which the system will be composed. The output format is typically an Electronic Design Interchange Format (EDIF) file.

There’s a large difference between compiling and synthesizing, and you have to stretch some to encompass it. Whereas the compiler produces bits to control fixed-gate patterns (the microprocessor decoders, registers, arithmetic logic unit, and so on) the synthesizer defines gate patterns described by the logic of the program. That is, your program logic gets synthesized, or mapped into, logical gates, not into processor instructions that control multigate structures. This is absolutely amazing, and good FPGA programmers give thanks every day for living in the rare time in history (post 1990+) when you can design architectures with words and then synthesize your logic into (mostly silicon) gates that execute your logic. Not to get carried away, but it’s absolutely wonderful.

Synthesis

 

The synthesis process produces bit patterns, in an intermediate format. We compile Verilog to TRL netlist, then synthesize Verilog to EDIF, then place and route EDIF to produce HEX or TTF files that can be loaded into an FPGA. These bit patterns will end up controlling logic gates and filling memory and registers.

The FPGA place and route process fits, in two dimensions, the bit patterns (logic subsystems) over a two dimensional array of available logic gates, and routes buses between these logic subsystems as necessary.

Loading

 

FPGA programs (compiled, synthesized, placed, and routed) must be embedded in the physical FPGAs. The actual programming file may be a .HEX or similar. Programmers typically download or burn the bits from these files into the hardware. If nonvolatile, this is a one-time proposition. If not, it’s a download-at-power-up proposition. 

Debugging program

All experienced programmers know that complex programs, even subprograms, don’t run correctly the first time. When we first see how to solve a problem, we tend to be overjoyed, (it’s possible!) and then underestimate the time required to implement the solution. This is because our powers of abstraction, based on experience, enable us to see solutions without worrying about every nitty-gritty detail. But the hard truth is that the physical system in which we’re embedding our programs requires that every nitty-gritty detail must be handled before it will work. No doubt, you have had the experience of fixing a single bit (or flag) that caused a crashing program to suddenly run correctly.

 

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