FPGA study note: Gate-level combinational circuit (2)

a 2-bit comparator


library ieee;
use ieee.std_logic_1164.all;
entity eq2 is 
     a, b: int std_logic_vector(1 downto 0);
     aeqb: out std_logic
end eq2;

architecture sop_arch of eq2 is 
    signal p0,p1,p2,p3: std_logic;
 -- sum of product terms
aeqb <= p0 or p1 or p2 or p3;
 -- product terms
  p0 <= ((not a(1)) and (not b(1))) and ((not a(0)) and not(b(0)));
  p1 <= ((not a(1)) and (not b(1))) and ((not a(0)) and not(b(0)));  
  p2 <= (a(1)) and b(1)) and ((not a(0)) and not(b(0)));
  p2 <= (a(1)) and b(1)) and (a(0)) and b(0));
end sop_arch;

and we can also use the previously constructed 1-bit comparators as a function.

architecture struc_arch of eq2 is 
    signal e0,e1: std_logic;
 -- onstantiate two 1-bit comparators
  eq_bit0_unit: entity work.eq1(sop_arch)
     port map(i0=>a(0),i1=>b(0),eq=>e0;
  eq_bit1_unit: entity work.eq1(sop_arch)
     port map(i0=>a(1),i1=>b(1),eq=>e1;
-- a and b are equal if individual bits are equal
aeqb <= e0 and e1;

In this code(line 6-9), the syntax of instantiation statements(VHDL 93)

 unit_label : entity lib_name.entity_name(arch_name)
   port map(
   formal_sinal => actual signal,
   formal_sinal => actual signal,
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