FPGA study note: Gate-level combinational circuit(3)

This is the last note of gate-level combination ciruit.  After code is developed, we have to verify the correctness of the circuit operation and to be synthesized to a physical device. we create a special program to simulate the physical lab bench, known as a testbench.

Alwalys start with code example:

library ieee;
use ieee.std_logic_1164.all;
entity eq2_testbench is 
end eq2_testbench;

architecture tb_arch of eq2_testbench is 
  signal test_in0, test_in1:std_logic_vector(1 to 0);
  signal test_out: std_logic;
 begin 
   uut:entity work.eq2(struc_arch)
       port map(a=>test_in0, b=>test_in1,aeqb=>test_out);
       process
       begin 
        test_in0 <= "00";
        test_in1 <= "00";
        wait for 200 ns;

        test_in0 <= "01";
        test_in1 <= "00";
        wait for 200 ns;

        test_in0 <= "01";
        test_in1 <= "11";
        wait for 200 ns;

        test_in0 <= "10";
        test_in1 <= "10";
        wait for 200 ns;

        test_in0 <= "10";
        test_in1 <= "00";
        wait for 200 ns;

        test_in0 <= "11";
        test_in1 <= "11";
        wait for 200 ns;

        test_in0 <= "11";
        test_in1 <= "01";
        wait for 200 ns;
     end process;
end tb_arch;

The process statement(from line 13 to 40) in this example is a special VHDL construct in which the operations are performed sequentially.

The input and output signal will be displayed on a “virtual logic analyzer”.

News Reporter
Dr. Lu

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