This figure shows the simplified development flow of an FPGA-based system.
The left portion of the flow is the refinement and programming process.
The Right portion is the validation process.
Several major steps in the flow are:
- Design the system and derive the HDL files.
- Develop the testbench in HDL and perform RTL simulation
- Perform synthesis and implementation.
- generate and download the programming fils.
In (3), the synthesis process is known as logic synthesis transforming HDL constract to generic gate-level components, ex logic gate or FFs. And translate, map and place and route constitute the next process implementation. These process can be automately performed by software.
if we follow good design and coding practices, the HDL code will be synthesized and implemented correctly. So We only need to use RTL simulation to check the correctness of the HDL code and use static timing analysis to the examinate the relevant timing informaiton. The functional simulation and timing simulation are optional. These optional simulations may require a significant amount of time to perform.