six relational operators are defined in the VHDL standard:
- /= not equal to
- <= less than or equal to
- >= greater than or equal to
we have to use these operator to compare the same data type and get the boolean data type.
IEEE numeric_std package: adds unsigned and signed data type.
library ieee; use ieee.std_logic_1164.all; use ieee.numric_std.all;
VHDL is a strongly typed language
So we need type conversion
the common mistakes and remedies for type conversion.
library ieee; use ieee.std_logic_1164.all; use ieee.numric_std.all; ... signal s1,s2,s3,s4,s5,s6 : std_logic_vector (3 downto 0); signal u1,u2,u3,u4,u5,u6 : unsigned (3 downto 0); ...
Considering the following assignment statements:
u1 <= s1; -- not ok u2 <= 5; -- not ok s2 <= u3; -- not ok s3 <= 5; -- not ok
Because the type mismatch, all these statement are invalied. The right-hand-side expression must be converted to the left-hand-side data type(std_logic_vector):
u1 <= unsigned(s1); -- type casting u2 <= to_unsigned(5,4); -- conversion function s2 <= std_logic_vector(u3); -- type casting s3 <= std_logic_vector(to_unsigned(5,4)); -- two type conversions
‘+’ is defined with the unsigned and natural types in the IEEE numric_std package.
u4 <= u2 + u1; --ok u5 <= u2 + 1; s5 <= s2 + s1; -- undefined over the types s6 <= s2 + 1; -- undefined over the types s5 <= std_logic_vector(unsigned (s2) + unsigned (s2)); -- ok s6 <= std_logic_vector(unsigned(s2) + 1); --ok
there are several non-IEEE standard arithmetic packages(not-recommanded):
- std_logiv_signed, which is similar to the numeric_std package