Concatenation operator:

signal a1: std_logic;
signal a4: std_logic_vector(3 downto 0);
signal b8,c8,d8: std_logic_vector(7 downto 0);
b8 <= a4 & a4;
c8 <= a1 & a1 & a4 & "00";
d8 <= b8(3 downto 0) & c8(3 downto 0);

The major application of ‘&’ operator is to perform shifting operation.
Ex. Code

signal a: std_logic_vector(7 downto 0);
signal rot,shl,sha: std_logic_vector(7 downto 0);
-- rotate a to right 3 bits
rot <= a(2 downto 0) & a(8 downto 3);
--shift a to right 3bits and insert 0(logic shift)
shl <= "000" & a(8 downto 3);
--shift a to right 3bits and insert MSB
--(arithmetic shift)
sha <= a(8) & a(8) & a(8) &a(8 downto 3);

The VHDL standard and numeric_std package also define shift functions, however, they sometimes cannot be synthesized automatically. The design of a barrel snifter will be discussed later.

News Reporter
Dr. Lu


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