‘Z’ value of std_logic implies high impedance of an open circuit. it can only be synthesized by a tri-state buffer shown as follow:

The buffer is controlled by an enable signal: when oe is ‘1’, the input is passed to output,otherwise, the y output appears to be an open circuit.

y <= a_in when oe='1' else 'Z';

The most common application for a tri-buffer is to implement a bidirectional port to better utilize a physical I/O pin as shown:


entity bi_demo is
     bi: input std_logic;
     sig_out <= output_expression;
     some_signal <= expression_with_sig_in;
     bi <= sig_out when dir ='1' else 'Z';
     sig_in <= bi;

Note that the mode of the bi port must be declared as inout for bidirectional operation.

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