Conditional signal assignment statement
Let’s start with simplified syntax of a conditional signal assignment:
signal_name <= value_expr_1 when boolean_expr_1 else; value_expr_2 when boolean_expr_2 else; ... value_expr_n;
The value_expr_n is assigned if all Boolean expressions are evaluated to be false.
r <= a+b+c when m=n else; a-b when m>n else; c+1;
The routing is done by a sequence of 2-to-1 multiplexers, shown as below:
All the Boolean expressions and value expressions are evaluated concurrently.
However, a large number of when-else clauses will lead to a long cascading chain and introduce a large propagation delay.
Function table of a four-request priority encoder
|input r||output pcode|
library ieee; use ieee.std_logic_1164.all; entity prio_encoder is port( r: in std_logic_vector(4 downto 1); pcode: out std_logic_vector(2 downto 0) ); end prio_encoder; architecture cond_arch of prio_encoder is begin pcode