FPGA study note: Constants and Generics (1)

Constants

HDL code frequently uses constant values in expressions and array boundaries. Replacing the “hard literals” with symbolic constants makes code clear and helps future maintenance and revision. The constant declaration can be included in the architecture’s declaration section.

Syntax:


constant const_name: data_type := value_expression;

Example:


constant DATA_BIT: integer := 8;
constatn DATA_RANGE: integer := 2**DATA_BIT -1 ;

Generally, we use capital letters for constants.

An adder with the carry-out bit


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity add_w_carry is 
  port(
        a,b: in std_logic_vector(3 downto 0);
        cout: out std_logic;
        sum: out std_logic_vector(3 downto 0);
    );
end add_w_carry;

architecture hard_arch of add_w_carry is
    signal a_ext, b_ext, sum_ext: unsigned( 4 downto 0);
    begin
        a_ext <= unsigned ('0' & a);
        b_ext <= unsigned ('0' & b);
        sum_ext <= a_ext + b_ext;   
        sum <= std_logic_vector(sum_ext(3 downto 0));
        cout <= sum_ext(4); 
    end hard_arch;   

This code is for a 4-bit adder. hard literals. If we want to revise the code for an 8-bit adder, these literals have to be modified manually.

If we use a symbolic constant, N, to represent the number of bits of the adder, as the following code, it makes the code easier to understand and maintain.


architecture const_arch of add_w_carry is 
    constant N: integer := 4;
    signal a_ext, b_ext, sum_ext: unsigned( N downto 0);
begin
        a_ext <= unsigned ('0' & a);
        b_ext <= unsigned ('0' & b);
        sum_ext <= a_ext + b_ext;  
        sum <= std_logic_vector(sum_ext(N-1 downto 0)); 
        cout <= sum_ext(N); 
end hard_arch; 
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Dr. Lu

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